thomas@1461
|
1 |
gcc svn 142778:
|
thomas@1461
|
2 |
|
thomas@1461
|
3 |
PR target/37436
|
thomas@1461
|
4 |
* arm.c (arm_legitimate_index): Only accept addresses that are in
|
thomas@1461
|
5 |
canonical form.
|
thomas@1461
|
6 |
* predicates.md (arm_reg_or_extendqisi_mem_op): New predicate.
|
thomas@1461
|
7 |
* arm.md (extendqihi2): Use arm_reg_or_extendqisi_mem_op predicate
|
thomas@1461
|
8 |
for operand1.
|
thomas@1461
|
9 |
(extendqisi2): Likewise.
|
thomas@1461
|
10 |
(arm_extendqisi, arm_extendqisi_v6): Use arm_extendqisi_mem_op
|
thomas@1461
|
11 |
predicate for operand1.
|
thomas@1461
|
12 |
|
thomas@1461
|
13 |
diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.c gcc-4.3.3/gcc/config/arm/arm.c
|
thomas@1461
|
14 |
--- gcc-4.3.3.orig/gcc/config/arm/arm.c 2008-06-11 07:52:55.000000000 -0300
|
thomas@1461
|
15 |
+++ gcc-4.3.3/gcc/config/arm/arm.c 2009-05-21 16:06:45.000000000 -0300
|
thomas@1461
|
16 |
@@ -3769,6 +3769,7 @@
|
thomas@1461
|
17 |
rtx xop1 = XEXP (x, 1);
|
thomas@1461
|
18 |
|
thomas@1461
|
19 |
return ((arm_address_register_rtx_p (xop0, strict_p)
|
thomas@1461
|
20 |
+ && GET_CODE(xop1) == CONST_INT
|
thomas@1461
|
21 |
&& arm_legitimate_index_p (mode, xop1, outer, strict_p))
|
thomas@1461
|
22 |
|| (arm_address_register_rtx_p (xop1, strict_p)
|
thomas@1461
|
23 |
&& arm_legitimate_index_p (mode, xop0, outer, strict_p)));
|
thomas@1461
|
24 |
diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.md gcc-4.3.3/gcc/config/arm/arm.md
|
thomas@1461
|
25 |
--- gcc-4.3.3.orig/gcc/config/arm/arm.md 2007-09-04 01:44:47.000000000 -0300
|
thomas@1461
|
26 |
+++ gcc-4.3.3/gcc/config/arm/arm.md 2009-05-21 16:06:45.000000000 -0300
|
thomas@1461
|
27 |
@@ -4199,7 +4199,7 @@
|
thomas@1461
|
28 |
|
thomas@1461
|
29 |
(define_expand "extendqihi2"
|
thomas@1461
|
30 |
[(set (match_dup 2)
|
thomas@1461
|
31 |
- (ashift:SI (match_operand:QI 1 "general_operand" "")
|
thomas@1461
|
32 |
+ (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
|
thomas@1461
|
33 |
(const_int 24)))
|
thomas@1461
|
34 |
(set (match_operand:HI 0 "s_register_operand" "")
|
thomas@1461
|
35 |
(ashiftrt:SI (match_dup 2)
|
thomas@1461
|
36 |
@@ -4224,7 +4224,7 @@
|
thomas@1461
|
37 |
|
thomas@1461
|
38 |
(define_insn "*arm_extendqihi_insn"
|
thomas@1461
|
39 |
[(set (match_operand:HI 0 "s_register_operand" "=r")
|
thomas@1461
|
40 |
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))]
|
thomas@1461
|
41 |
+ (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
|
thomas@1461
|
42 |
"TARGET_ARM && arm_arch4"
|
thomas@1461
|
43 |
"ldr%(sb%)\\t%0, %1"
|
thomas@1461
|
44 |
[(set_attr "type" "load_byte")
|
thomas@1461
|
45 |
@@ -4235,7 +4235,7 @@
|
thomas@1461
|
46 |
|
thomas@1461
|
47 |
(define_expand "extendqisi2"
|
thomas@1461
|
48 |
[(set (match_dup 2)
|
thomas@1461
|
49 |
- (ashift:SI (match_operand:QI 1 "general_operand" "")
|
thomas@1461
|
50 |
+ (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
|
thomas@1461
|
51 |
(const_int 24)))
|
thomas@1461
|
52 |
(set (match_operand:SI 0 "s_register_operand" "")
|
thomas@1461
|
53 |
(ashiftrt:SI (match_dup 2)
|
thomas@1461
|
54 |
@@ -4267,7 +4267,7 @@
|
thomas@1461
|
55 |
|
thomas@1461
|
56 |
(define_insn "*arm_extendqisi"
|
thomas@1461
|
57 |
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
thomas@1461
|
58 |
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))]
|
thomas@1461
|
59 |
+ (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
|
thomas@1461
|
60 |
"TARGET_ARM && arm_arch4 && !arm_arch6"
|
thomas@1461
|
61 |
"ldr%(sb%)\\t%0, %1"
|
thomas@1461
|
62 |
[(set_attr "type" "load_byte")
|
thomas@1461
|
63 |
@@ -4278,7 +4278,8 @@
|
thomas@1461
|
64 |
|
thomas@1461
|
65 |
(define_insn "*arm_extendqisi_v6"
|
thomas@1461
|
66 |
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
thomas@1461
|
67 |
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))]
|
thomas@1461
|
68 |
+ (sign_extend:SI
|
thomas@1461
|
69 |
+ (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
|
thomas@1461
|
70 |
"TARGET_ARM && arm_arch6"
|
thomas@1461
|
71 |
"@
|
thomas@1461
|
72 |
sxtb%?\\t%0, %1
|
thomas@1461
|
73 |
diff -Nura gcc-4.3.3.orig/gcc/config/arm/predicates.md gcc-4.3.3/gcc/config/arm/predicates.md
|
thomas@1461
|
74 |
--- gcc-4.3.3.orig/gcc/config/arm/predicates.md 2007-08-02 07:49:31.000000000 -0300
|
thomas@1461
|
75 |
+++ gcc-4.3.3/gcc/config/arm/predicates.md 2009-05-21 16:06:45.000000000 -0300
|
thomas@1461
|
76 |
@@ -234,6 +234,10 @@
|
thomas@1461
|
77 |
(match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
|
thomas@1461
|
78 |
0)")))
|
thomas@1461
|
79 |
|
thomas@1461
|
80 |
+(define_special_predicate "arm_reg_or_extendqisi_mem_op"
|
thomas@1461
|
81 |
+ (ior (match_operand 0 "arm_extendqisi_mem_op")
|
thomas@1461
|
82 |
+ (match_operand 0 "s_register_operand")))
|
thomas@1461
|
83 |
+
|
thomas@1461
|
84 |
(define_predicate "power_of_two_operand"
|
thomas@1461
|
85 |
(match_code "const_int")
|
thomas@1461
|
86 |
{
|