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patches/glibc/2.9/530-powerpc-8xx-CPU15-errata.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Sat Dec 31 18:47:37 2011 +0100 (2011-12-31)
changeset 2829 0c3c95f911ec
parent 1016 a059741f7bd4
permissions -rw-r--r--
docs: credit Konrad EISELE for the initial multilib support

Konrad submitted an initial patch adding multlib support:
http://sourceware.org/ml/crossgcc/2011-11/msg00040.html

The patch was full of good ideas, but had a few issues, so
I (Yann E. MORIN) started it all from scatch, re-using part
of the original patch. This got implemented in this series:
hg log -r 446a17b5dd1e:e47d17391ae3

As I forgot to credit Konrad in these changelogs, update the
docs so that the work by Konrad gets credited. Without his
initial effort, we would probably not have had multlib support
so soon. Thank you Konrad!

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr> 
     1 Fix memset on PowerPC 8xx, by Nye Liu:

     2 http://sourceware.org/ml/crossgcc/2008-10/msg00067.html

     3 

     4 Quote:

     5  I am working on a powerpc 860 toolchain, but I am having problems  

     6  convincing glibc to not emit code that uses the dcbz instruction (CPU15  

     7  dcbX bug). The source of the problem is sysdeps/powerpc/power3/memset.S

     8 

     9 --- glibc-2.7/sysdeps/powerpc/powerpc32/memset.S	2007-03-26 13:09:07.000000000 -0700

    10 +++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new	2008-10-23 20:28:52.000000000 -0700

    11 @@ -112,11 +112,13 @@

    12  	clrrwi.	rALIGN, rLEN, 5

    13  	mtcrf	0x01, rLEN	/* 40th instruction from .align */

    14  

    15 +#ifndef BROKEN_PPC_8xx_CPU15

    16  /* Check if we can use the special case for clearing memory using dcbz.

    17     This requires that we know the correct cache line size for this

    18     processor.  Getting the __cache_line_size may require establishing GOT

    19     addressability, so branch out of line to set this up.  */

    20  	beq	cr1, L(checklinesize)

    21 +#endif

    22  

    23  /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.

    24     Can't assume that rCHR is zero or that the cache line size is either

    25 @@ -158,6 +160,7 @@

    26  	add	rMEMP, rMEMP, rALIGN

    27  	b	L(medium_tail2)	/* 72nd instruction from .align */

    28  

    29 +#ifndef BROKEN_PPC_8xx_CPU15

    30  	.align	5

    31  	nop

    32  /* Clear cache lines of memory in 128-byte chunks.

    33 @@ -191,6 +194,7 @@

    34  	bdnz	L(zloop)

    35  	beqlr	cr5

    36  	b	L(medium_tail2)

    37 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    38  

    39  	.align	5

    40  L(small):

    41 @@ -248,6 +252,7 @@

    42  	stw	rCHR, -8(rMEMP)

    43  	blr

    44  

    45 +#ifndef BROKEN_PPC_8xx_CPU15

    46  L(checklinesize):

    47  #ifdef SHARED

    48  	mflr	rTMP

    49 @@ -329,6 +334,7 @@

    50  L(handletail32):

    51  	clrrwi.	rALIGN, rLEN, 5

    52  	b	L(nondcbz)

    53 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    54  

    55  END (BP_SYM (memset))

    56  libc_hidden_builtin_def (memset)
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