1 --- glibc-2.1.3/stdlib/longlong.h.old 2004-03-05 14:49:14.000000000 -0800
2 +++ glibc-2.1.3/stdlib/longlong.h 2004-03-05 15:19:26.000000000 -0800
5 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
6 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
7 - __asm__ ("add %1,%4,%5
9 + __asm__ ("add %1,%4,%5\n" \
11 : "=r" ((USItype)(sh)), \
12 "=&r" ((USItype)(sl)) \
13 : "%r" ((USItype)(ah)), \
15 "%r" ((USItype)(al)), \
17 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
18 - __asm__ ("sub %1,%4,%5
20 + __asm__ ("sub %1,%4,%5\n" \
22 : "=r" ((USItype)(sh)), \
23 "=&r" ((USItype)(sl)) \
24 : "r" ((USItype)(ah)), \
27 #if defined (__arm__) && W_TYPE_SIZE == 32
28 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
29 - __asm__ ("adds %1, %4, %5
31 + __asm__ ("adds %1, %4, %5\n" \
33 : "=r" ((USItype)(sh)), \
34 "=&r" ((USItype)(sl)) \
35 : "%r" ((USItype)(ah)), \
37 "%r" ((USItype)(al)), \
39 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
40 - __asm__ ("subs %1, %4, %5
42 + __asm__ ("subs %1, %4, %5\n" \
44 : "=r" ((USItype)(sh)), \
45 "=&r" ((USItype)(sl)) \
46 : "r" ((USItype)(ah)), \
50 #define umul_ppmm(xh, xl, a, b) \
51 - __asm__ ("%@ Inlined umul_ppmm
52 - mov %|r0, %2, lsr #16
53 - mov %|r2, %3, lsr #16
54 - bic %|r1, %2, %|r0, lsl #16
55 - bic %|r2, %3, %|r2, lsl #16
57 - mul %|r2, %|r0, %|r2
60 - adds %|r1, %|r2, %|r1
61 - addcs %0, %0, #65536
62 - adds %1, %1, %|r1, lsl #16
63 - adc %0, %0, %|r1, lsr #16" \
64 + __asm__ ("%@ Inlined umul_ppmm\n" \
65 + "mov %|r0, %2, lsr #16\n" \
66 + "mov %|r2, %3, lsr #16\n" \
67 + "bic %|r1, %2, %|r0, lsl #16\n" \
68 + "bic %|r2, %3, %|r2, lsl #16\n" \
69 + "mul %1, %|r1, %|r2\n" \
70 + "mul %|r2, %|r0, %|r2\n" \
71 + "mul %|r1, %0, %|r1\n" \
72 + "mul %0, %|r0, %0\n" \
73 + "adds %|r1, %|r2, %|r1\n" \
74 + "addcs %0, %0, #65536\n" \
75 + "adds %1, %1, %|r1, lsl #16\n" \
76 + "adc %0, %0, %|r1, lsr #16" \
77 : "=&r" ((USItype)(xh)), \
78 "=r" ((USItype)(xl)) \
79 : "r" ((USItype)(a)), \
82 #if defined (__gmicro__) && W_TYPE_SIZE == 32
83 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
84 - __asm__ ("add.w %5,%1
86 + __asm__ ("add.w %5,%1\n" \
88 : "=g" ((USItype)(sh)), \
89 "=&g" ((USItype)(sl)) \
90 : "%0" ((USItype)(ah)), \
92 "%1" ((USItype)(al)), \
94 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
95 - __asm__ ("sub.w %5,%1
97 + __asm__ ("sub.w %5,%1\n" \
99 : "=g" ((USItype)(sh)), \
100 "=&g" ((USItype)(sl)) \
101 : "0" ((USItype)(ah)), \
104 #if defined (__hppa) && W_TYPE_SIZE == 32
105 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
106 - __asm__ ("add %4,%5,%1
108 + __asm__ ("add %4,%5,%1\n" \
110 : "=r" ((USItype)(sh)), \
111 "=&r" ((USItype)(sl)) \
112 : "%rM" ((USItype)(ah)), \
114 "%rM" ((USItype)(al)), \
115 "rM" ((USItype)(bl)))
116 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
117 - __asm__ ("sub %4,%5,%1
119 + __asm__ ("sub %4,%5,%1\n" \
121 : "=r" ((USItype)(sh)), \
122 "=&r" ((USItype)(sl)) \
123 : "rM" ((USItype)(ah)), \
124 @@ -332,22 +332,22 @@
129 - extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
130 - extru,tr %1,15,16,%1 ; No. Shift down, skip add.
131 - ldo 16(%0),%0 ; Yes. Perform add.
132 - extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
133 - extru,tr %1,23,8,%1 ; No. Shift down, skip add.
134 - ldo 8(%0),%0 ; Yes. Perform add.
135 - extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
136 - extru,tr %1,27,4,%1 ; No. Shift down, skip add.
137 - ldo 4(%0),%0 ; Yes. Perform add.
138 - extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
139 - extru,tr %1,29,2,%1 ; No. Shift down, skip add.
140 - ldo 2(%0),%0 ; Yes. Perform add.
141 - extru %1,30,1,%1 ; Extract bit 1.
142 - sub %0,%1,%0 ; Subtract it.
143 - " : "=r" (count), "=r" (__tmp) : "1" (x)); \
145 + "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
146 + "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
147 + "ldo 16(%0),%0 ; Yes. Perform add.\n" \
148 + "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
149 + "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
150 + "ldo 8(%0),%0 ; Yes. Perform add.\n" \
151 + "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
152 + "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
153 + "ldo 4(%0),%0 ; Yes. Perform add.\n" \
154 + "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
155 + "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
156 + "ldo 2(%0),%0 ; Yes. Perform add.\n" \
157 + "extru %1,30,1,%1 ; Extract bit 1.\n" \
158 + "sub %0,%1,%0 ; Subtract it.\n" \
159 + : "=r" (count), "=r" (__tmp) : "1" (x)); \
165 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
166 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
167 - __asm__ ("addl %5,%1
169 + __asm__ ("addl %5,%1\n" \
171 : "=r" ((USItype)(sh)), \
172 "=&r" ((USItype)(sl)) \
173 : "%0" ((USItype)(ah)), \
175 "%1" ((USItype)(al)), \
177 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
178 - __asm__ ("subl %5,%1
180 + __asm__ ("subl %5,%1\n" \
182 : "=r" ((USItype)(sh)), \
183 "=&r" ((USItype)(sl)) \
184 : "0" ((USItype)(ah)), \
187 #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
188 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
189 - __asm__ ("add%.l %5,%1
191 + __asm__ ("add%.l %5,%1\n" \
193 : "=d" ((USItype)(sh)), \
194 "=&d" ((USItype)(sl)) \
195 : "%0" ((USItype)(ah)), \
197 "%1" ((USItype)(al)), \
199 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
200 - __asm__ ("sub%.l %5,%1
202 + __asm__ ("sub%.l %5,%1\n" \
204 : "=d" ((USItype)(sh)), \
205 "=&d" ((USItype)(sl)) \
206 : "0" ((USItype)(ah)), \
207 @@ -564,28 +564,28 @@
208 #else /* not mc68020 */
209 #define umul_ppmm(xh, xl, a, b) \
210 do { USItype __umul_tmp1, __umul_tmp2; \
211 - __asm__ ("| Inlined umul_ppmm
224 - add%.l %#0x10000,%0
232 - | End inlined umul_ppmm" \
233 + __asm__ ("| Inlined umul_ppmm\n" \
234 + "move%.l %5,%3\n" \
235 + "move%.l %2,%0\n" \
236 + "move%.w %3,%1\n" \
246 + "add%.l %#0x10000,%0\n" \
247 +"1: move%.l %2,%3\n" \
253 + "addx%.l %2,%0\n" \
254 + "| End inlined umul_ppmm" \
255 : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
256 "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
257 : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
260 #if defined (__m88000__) && W_TYPE_SIZE == 32
261 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
262 - __asm__ ("addu.co %1,%r4,%r5
263 - addu.ci %0,%r2,%r3" \
264 + __asm__ ("addu.co %1,%r4,%r5\n" \
265 + "addu.ci %0,%r2,%r3" \
266 : "=r" ((USItype)(sh)), \
267 "=&r" ((USItype)(sl)) \
268 : "%rJ" ((USItype)(ah)), \
270 "%rJ" ((USItype)(al)), \
271 "rJ" ((USItype)(bl)))
272 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
273 - __asm__ ("subu.co %1,%r4,%r5
274 - subu.ci %0,%r2,%r3" \
275 + __asm__ ("subu.co %1,%r4,%r5\n" \
276 + "subu.ci %0,%r2,%r3" \
277 : "=r" ((USItype)(sh)), \
278 "=&r" ((USItype)(sl)) \
279 : "rJ" ((USItype)(ah)), \
283 #define umul_ppmm(w1, w0, u, v) \
284 - __asm__ ("multu %2,%3
287 + __asm__ ("multu %2,%3\n" \
290 : "=d" ((USItype)(w0)), \
291 "=d" ((USItype)(w1)) \
292 : "d" ((USItype)(u)), \
296 #define umul_ppmm(w1, w0, u, v) \
297 - __asm__ ("dmultu %2,%3
300 + __asm__ ("dmultu %2,%3\n" \
303 : "=d" ((UDItype)(w0)), \
304 "=d" ((UDItype)(w1)) \
305 : "d" ((UDItype)(u)), \
308 #if defined (__pyr__) && W_TYPE_SIZE == 32
309 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
310 - __asm__ ("addw %5,%1
312 + __asm__ ("addw %5,%1\n" \
314 : "=r" ((USItype)(sh)), \
315 "=&r" ((USItype)(sl)) \
316 : "%0" ((USItype)(ah)), \
318 "%1" ((USItype)(al)), \
320 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
321 - __asm__ ("subw %5,%1
323 + __asm__ ("subw %5,%1\n" \
325 : "=r" ((USItype)(sh)), \
326 "=&r" ((USItype)(sl)) \
327 : "0" ((USItype)(ah)), \
329 ({union {UDItype __ll; \
330 struct {USItype __h, __l;} __i; \
332 - __asm__ ("movw %1,%R0
334 + __asm__ ("movw %1,%R0\n" \
336 : "=&r" (__xx.__ll) \
337 : "g" ((USItype) (u)), \
338 "g" ((USItype)(v))); \
341 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
342 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
345 + __asm__ ("a %1,%5\n" \
347 : "=r" ((USItype)(sh)), \
348 "=&r" ((USItype)(sl)) \
349 : "%0" ((USItype)(ah)), \
351 "%1" ((USItype)(al)), \
353 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
356 + __asm__ ("s %1,%5\n" \
358 : "=r" ((USItype)(sh)), \
359 "=&r" ((USItype)(sl)) \
360 : "0" ((USItype)(ah)), \
361 @@ -910,26 +910,26 @@
363 USItype __m0 = (m0), __m1 = (m1); \
405 : "=r" ((USItype)(ph)), \
406 "=r" ((USItype)(pl)) \
409 #if defined (__sh2__) && W_TYPE_SIZE == 32
410 #define umul_ppmm(w1, w0, u, v) \
415 + "dmulu.l %2,%3\n" \
418 : "=r" ((USItype)(w1)), \
419 "=r" ((USItype)(w0)) \
420 : "r" ((USItype)(u)), \
423 #if defined (__sparc__) && W_TYPE_SIZE == 32
424 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
425 - __asm__ ("addcc %r4,%5,%1
427 + __asm__ ("addcc %r4,%5,%1\n" \
429 : "=r" ((USItype)(sh)), \
430 "=&r" ((USItype)(sl)) \
431 : "%rJ" ((USItype)(ah)), \
433 "rI" ((USItype)(bl)) \
435 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
436 - __asm__ ("subcc %r4,%5,%1
438 + __asm__ ("subcc %r4,%5,%1\n" \
440 : "=r" ((USItype)(sh)), \
441 "=&r" ((USItype)(sl)) \
442 : "rJ" ((USItype)(ah)), \
443 @@ -1029,45 +1029,45 @@
446 #define udiv_qrnnd(q, r, n1, n0, d) \
447 - __asm__ ("! Inlined udiv_qrnnd
448 - wr %%g0,%2,%%y ! Not a delayed write for sparclite
451 - divscc %%g1,%4,%%g1
452 - divscc %%g1,%4,%%g1
453 - divscc %%g1,%4,%%g1
454 - divscc %%g1,%4,%%g1
455 - divscc %%g1,%4,%%g1
456 - divscc %%g1,%4,%%g1
457 - divscc %%g1,%4,%%g1
458 - divscc %%g1,%4,%%g1
459 - divscc %%g1,%4,%%g1
460 - divscc %%g1,%4,%%g1
461 - divscc %%g1,%4,%%g1
462 - divscc %%g1,%4,%%g1
463 - divscc %%g1,%4,%%g1
464 - divscc %%g1,%4,%%g1
465 - divscc %%g1,%4,%%g1
466 - divscc %%g1,%4,%%g1
467 - divscc %%g1,%4,%%g1
468 - divscc %%g1,%4,%%g1
469 - divscc %%g1,%4,%%g1
470 - divscc %%g1,%4,%%g1
471 - divscc %%g1,%4,%%g1
472 - divscc %%g1,%4,%%g1
473 - divscc %%g1,%4,%%g1
474 - divscc %%g1,%4,%%g1
475 - divscc %%g1,%4,%%g1
476 - divscc %%g1,%4,%%g1
477 - divscc %%g1,%4,%%g1
478 - divscc %%g1,%4,%%g1
479 - divscc %%g1,%4,%%g1
480 - divscc %%g1,%4,%%g1
485 -1: ! End of inline udiv_qrnnd" \
486 + __asm__ ("! Inlined udiv_qrnnd\n" \
487 + "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
489 + "divscc %3,%4,%%g1\n" \
490 + "divscc %%g1,%4,%%g1\n" \
491 + "divscc %%g1,%4,%%g1\n" \
492 + "divscc %%g1,%4,%%g1\n" \
493 + "divscc %%g1,%4,%%g1\n" \
494 + "divscc %%g1,%4,%%g1\n" \
495 + "divscc %%g1,%4,%%g1\n" \
496 + "divscc %%g1,%4,%%g1\n" \
497 + "divscc %%g1,%4,%%g1\n" \
498 + "divscc %%g1,%4,%%g1\n" \
499 + "divscc %%g1,%4,%%g1\n" \
500 + "divscc %%g1,%4,%%g1\n" \
501 + "divscc %%g1,%4,%%g1\n" \
502 + "divscc %%g1,%4,%%g1\n" \
503 + "divscc %%g1,%4,%%g1\n" \
504 + "divscc %%g1,%4,%%g1\n" \
505 + "divscc %%g1,%4,%%g1\n" \
506 + "divscc %%g1,%4,%%g1\n" \
507 + "divscc %%g1,%4,%%g1\n" \
508 + "divscc %%g1,%4,%%g1\n" \
509 + "divscc %%g1,%4,%%g1\n" \
510 + "divscc %%g1,%4,%%g1\n" \
511 + "divscc %%g1,%4,%%g1\n" \
512 + "divscc %%g1,%4,%%g1\n" \
513 + "divscc %%g1,%4,%%g1\n" \
514 + "divscc %%g1,%4,%%g1\n" \
515 + "divscc %%g1,%4,%%g1\n" \
516 + "divscc %%g1,%4,%%g1\n" \
517 + "divscc %%g1,%4,%%g1\n" \
518 + "divscc %%g1,%4,%%g1\n" \
519 + "divscc %%g1,%4,%%g1\n" \
520 + "divscc %%g1,%4,%0\n" \
524 +"1: ! End of inline udiv_qrnnd" \
525 : "=r" ((USItype)(q)), \
526 "=r" ((USItype)(r)) \
527 : "r" ((USItype)(n1)), \
528 @@ -1087,46 +1087,46 @@
529 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
531 #define umul_ppmm(w1, w0, u, v) \
532 - __asm__ ("! Inlined umul_ppmm
533 - wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
534 - sra %3,31,%%g2 ! Don't move this insn
535 - and %2,%%g2,%%g2 ! Don't move this insn
536 - andcc %%g0,0,%%g1 ! Don't move this insn
537 - mulscc %%g1,%3,%%g1
538 - mulscc %%g1,%3,%%g1
539 - mulscc %%g1,%3,%%g1
540 - mulscc %%g1,%3,%%g1
541 - mulscc %%g1,%3,%%g1
542 - mulscc %%g1,%3,%%g1
543 - mulscc %%g1,%3,%%g1
544 - mulscc %%g1,%3,%%g1
545 - mulscc %%g1,%3,%%g1
546 - mulscc %%g1,%3,%%g1
547 - mulscc %%g1,%3,%%g1
548 - mulscc %%g1,%3,%%g1
549 - mulscc %%g1,%3,%%g1
550 - mulscc %%g1,%3,%%g1
551 - mulscc %%g1,%3,%%g1
552 - mulscc %%g1,%3,%%g1
553 - mulscc %%g1,%3,%%g1
554 - mulscc %%g1,%3,%%g1
555 - mulscc %%g1,%3,%%g1
556 - mulscc %%g1,%3,%%g1
557 - mulscc %%g1,%3,%%g1
558 - mulscc %%g1,%3,%%g1
559 - mulscc %%g1,%3,%%g1
560 - mulscc %%g1,%3,%%g1
561 - mulscc %%g1,%3,%%g1
562 - mulscc %%g1,%3,%%g1
563 - mulscc %%g1,%3,%%g1
564 - mulscc %%g1,%3,%%g1
565 - mulscc %%g1,%3,%%g1
566 - mulscc %%g1,%3,%%g1
567 - mulscc %%g1,%3,%%g1
568 - mulscc %%g1,%3,%%g1
572 + __asm__ ("! Inlined umul_ppmm\n" \
573 + "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
574 + "sra %3,31,%%g2 ! Don't move this insn\n" \
575 + "and %2,%%g2,%%g2 ! Don't move this insn\n" \
576 + "andcc %%g0,0,%%g1 ! Don't move this insn\n" \
577 + "mulscc %%g1,%3,%%g1\n" \
578 + "mulscc %%g1,%3,%%g1\n" \
579 + "mulscc %%g1,%3,%%g1\n" \
580 + "mulscc %%g1,%3,%%g1\n" \
581 + "mulscc %%g1,%3,%%g1\n" \
582 + "mulscc %%g1,%3,%%g1\n" \
583 + "mulscc %%g1,%3,%%g1\n" \
584 + "mulscc %%g1,%3,%%g1\n" \
585 + "mulscc %%g1,%3,%%g1\n" \
586 + "mulscc %%g1,%3,%%g1\n" \
587 + "mulscc %%g1,%3,%%g1\n" \
588 + "mulscc %%g1,%3,%%g1\n" \
589 + "mulscc %%g1,%3,%%g1\n" \
590 + "mulscc %%g1,%3,%%g1\n" \
591 + "mulscc %%g1,%3,%%g1\n" \
592 + "mulscc %%g1,%3,%%g1\n" \
593 + "mulscc %%g1,%3,%%g1\n" \
594 + "mulscc %%g1,%3,%%g1\n" \
595 + "mulscc %%g1,%3,%%g1\n" \
596 + "mulscc %%g1,%3,%%g1\n" \
597 + "mulscc %%g1,%3,%%g1\n" \
598 + "mulscc %%g1,%3,%%g1\n" \
599 + "mulscc %%g1,%3,%%g1\n" \
600 + "mulscc %%g1,%3,%%g1\n" \
601 + "mulscc %%g1,%3,%%g1\n" \
602 + "mulscc %%g1,%3,%%g1\n" \
603 + "mulscc %%g1,%3,%%g1\n" \
604 + "mulscc %%g1,%3,%%g1\n" \
605 + "mulscc %%g1,%3,%%g1\n" \
606 + "mulscc %%g1,%3,%%g1\n" \
607 + "mulscc %%g1,%3,%%g1\n" \
608 + "mulscc %%g1,%3,%%g1\n" \
609 + "mulscc %%g1,0,%%g1\n" \
610 + "add %%g1,%%g2,%0\n" \
612 : "=r" ((USItype)(w1)), \
613 "=r" ((USItype)(w0)) \
614 : "%rI" ((USItype)(u)), \
615 @@ -1138,30 +1138,30 @@
616 /* It's quite necessary to add this much assembler for the sparc.
617 The default udiv_qrnnd (in C) is more than 10 times slower! */
618 #define udiv_qrnnd(q, r, n1, n0, d) \
619 - __asm__ ("! Inlined udiv_qrnnd
623 - addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
624 - sub %1,%2,%1 ! this kills msb of n
625 - addx %1,%1,%1 ! so this can't give carry
630 - addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
632 - sub %1,%2,%1 ! this kills msb of n
637 -! Got carry from n. Subtract next step to cancel this carry.
639 - addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
642 - ! End of inline udiv_qrnnd" \
643 + __asm__ ("! Inlined udiv_qrnnd\n" \
645 + "subcc %1,%2,%%g0\n" \
647 + "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
648 + "sub %1,%2,%1 ! this kills msb of n\n" \
649 + "addx %1,%1,%1 ! so this can't give carry\n" \
650 + "subcc %%g1,1,%%g1\n" \
652 + "subcc %1,%2,%%g0\n" \
654 + "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
656 + "sub %1,%2,%1 ! this kills msb of n\n" \
657 +"4: sub %1,%2,%1\n" \
658 +"5: addxcc %1,%1,%1\n" \
660 + "subcc %%g1,1,%%g1\n" \
661 +"! Got carry from n. Subtract next step to cancel this carry.\n" \
663 + "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
665 +"3: xnor %0,0,%0\n" \
666 + "! End of inline udiv_qrnnd" \
667 : "=&r" ((USItype)(q)), \
668 "=&r" ((USItype)(r)) \
669 : "r" ((USItype)(d)), \
670 @@ -1179,11 +1179,11 @@
671 #if (defined (__sparc_v9__) || (defined (__sparc__) && defined (__arch64__)) \
672 || defined (__sparcv9)) && W_TYPE_SIZE == 64
673 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
674 - __asm__ ("addcc %r4,%5,%1
679 + __asm__ ("addcc %r4,%5,%1\n" \
680 + "add %r2,%3,%0\n" \
681 + "bcs,a,pn %%xcc, 1f\n" \
682 + "add %0, 1, %0\n" \
684 : "=r" ((UDItype)(sh)), \
685 "=&r" ((UDItype)(sl)) \
686 : "r" ((UDItype)(ah)), \
687 @@ -1193,11 +1193,11 @@
690 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
691 - __asm__ ("subcc %r4,%5,%1
696 + __asm__ ("subcc %r4,%5,%1\n" \
697 + "sub %r2,%3,%0\n" \
698 + "bcs,a,pn %%xcc, 1f\n" \
699 + "sub %0, 1, %0\n" \
701 : "=r" ((UDItype)(sh)), \
702 "=&r" ((UDItype)(sl)) \
703 : "r" ((UDItype)(ah)), \
704 @@ -1210,27 +1210,27 @@
706 UDItype tmp1, tmp2, tmp3, tmp4; \
707 __asm__ __volatile__ ( \
720 - sethi %%hi(0x80000000),%2
724 - movcc %%xcc,%%g0,%2
730 + "mulx %3,%6,%1\n" \
731 + "srlx %6,32,%2\n" \
732 + "mulx %2,%3,%4\n" \
733 + "sllx %4,32,%5\n" \
736 + "srlx %5,32,%5\n" \
737 + "addcc %4,%5,%4\n" \
738 + "srlx %7,32,%5\n" \
739 + "mulx %3,%5,%3\n" \
740 + "mulx %2,%5,%5\n" \
741 + "sethi %%hi(0x80000000),%2\n" \
742 + "addcc %4,%3,%4\n" \
743 + "srlx %4,32,%4\n" \
745 + "movcc %%xcc,%%g0,%2\n" \
746 + "addcc %5,%4,%5\n" \
747 + "sllx %3,32,%3\n" \
750 : "=r" ((UDItype)(wh)), \
751 "=&r" ((UDItype)(wl)), \
752 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
753 @@ -1244,8 +1244,8 @@
755 #if defined (__vax__) && W_TYPE_SIZE == 32
756 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
757 - __asm__ ("addl2 %5,%1
759 + __asm__ ("addl2 %5,%1\n" \
761 : "=g" ((USItype)(sh)), \
762 "=&g" ((USItype)(sl)) \
763 : "%0" ((USItype)(ah)), \
764 @@ -1253,8 +1253,8 @@
765 "%1" ((USItype)(al)), \
767 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
768 - __asm__ ("subl2 %5,%1
770 + __asm__ ("subl2 %5,%1\n" \
772 : "=g" ((USItype)(sh)), \
773 "=&g" ((USItype)(sl)) \
774 : "0" ((USItype)(ah)), \