Introduce target-specific LDFLAGS, the same way we have CFLAGS for the target.
It seems to be helping gcc somewhat into telling the correct endianness to ld that sticks with little endian even when the target is big (eg armeb-unknown-linux-uclibcgnueabi).
There's still work to do, especially finish the gcc part that is not in this commit.
/trunk/scripts/functions | 9 7 2 0 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
3 In file included from include/asm/thread_info.h:16,
4 from include/linux/thread_info.h:21,
5 from include/linux/spinlock.h:12,
6 from include/linux/capability.h:45,
7 from include/linux/sched.h:7,
8 from arch/i386/kernel/asm-offsets.c:7:
9 include/asm/processor.h:87: error: array type has incomplete element type
10 make[1]: *** [arch/i386/kernel/asm-offsets.asm] Error 1
12 --- linux-2.6.8/include/asm-i386/processor.h.old Tue Mar 15 00:14:42 2005
13 +++ linux-2.6.8/include/asm-i386/processor.h Tue Mar 15 00:18:45 2005
15 #define X86_VENDOR_UNKNOWN 0xff
18 + * Size of io_bitmap.
20 +#define IO_BITMAP_BITS 65536
21 +#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
22 +#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
23 +#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
24 +#define INVALID_IO_BITMAP_OFFSET 0x8000
27 + unsigned short back_link,__blh;
29 + unsigned short ss0,__ss0h;
31 + unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
33 + unsigned short ss2,__ss2h;
34 + unsigned long __cr3;
36 + unsigned long eflags;
37 + unsigned long eax,ecx,edx,ebx;
42 + unsigned short es, __esh;
43 + unsigned short cs, __csh;
44 + unsigned short ss, __ssh;
45 + unsigned short ds, __dsh;
46 + unsigned short fs, __fsh;
47 + unsigned short gs, __gsh;
48 + unsigned short ldt, __ldth;
49 + unsigned short trace, io_bitmap_base;
51 + * The extra 1 is there because the CPU will access an
52 + * additional byte beyond the end of the IO permission
53 + * bitmap. The extra byte must be all 1 bits, and must
54 + * be within the limit.
56 + unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
58 + * pads the TSS to be cacheline-aligned (size is 0x100)
60 + unsigned long __cacheline_filler[37];
62 + * .. and then another 0x100 bytes for emergency kernel stack
64 + unsigned long stack[64];
65 +} __attribute__((packed));
67 +#define ARCH_MIN_TASKALIGN 16
70 * capabilities of CPUs
75 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
78 - * Size of io_bitmap.
80 -#define IO_BITMAP_BITS 65536
81 -#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
82 -#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
83 -#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
84 -#define INVALID_IO_BITMAP_OFFSET 0x8000
86 struct i387_fsave_struct {
95 - unsigned short back_link,__blh;
97 - unsigned short ss0,__ss0h;
99 - unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
100 - unsigned long esp2;
101 - unsigned short ss2,__ss2h;
102 - unsigned long __cr3;
104 - unsigned long eflags;
105 - unsigned long eax,ecx,edx,ebx;
110 - unsigned short es, __esh;
111 - unsigned short cs, __csh;
112 - unsigned short ss, __ssh;
113 - unsigned short ds, __dsh;
114 - unsigned short fs, __fsh;
115 - unsigned short gs, __gsh;
116 - unsigned short ldt, __ldth;
117 - unsigned short trace, io_bitmap_base;
119 - * The extra 1 is there because the CPU will access an
120 - * additional byte beyond the end of the IO permission
121 - * bitmap. The extra byte must be all 1 bits, and must
122 - * be within the limit.
124 - unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
126 - * pads the TSS to be cacheline-aligned (size is 0x100)
128 - unsigned long __cacheline_filler[37];
130 - * .. and then another 0x100 bytes for emergency kernel stack
132 - unsigned long stack[64];
133 -} __attribute__((packed));
135 -#define ARCH_MIN_TASKALIGN 16
137 struct thread_struct {
138 /* cached TLS descriptors. */