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patches/eglibc/2_10/100-powerpc-8xx-CPU15-errata.patch
author Anthony Foiani <anthony.foiani@gmail.com>
Thu May 19 23:09:43 2011 +0200 (2011-05-19)
branch1.11
changeset 2465 5f98b7a90fbc
parent 1328 f9e0931908f4
permissions -rw-r--r--
complibs/ppl: fix 0.11-0.11.2 to compile with --disable-shared

PPL 0.11 (through 0.11.2) had a small bug where it still tried to build
and test its Java interface even when shared libraries are disabled.
Since that's exactly what ct-ng does, it explodes.

This is the patch from the PPL authors (see final link below).

More information can be found in these messages/threads:

Anthony's initial report and analysis with Yann:
http://www.cygwin.com/ml/crossgcc/2011-05/msg00046.html

Ron Flory hit the same problem:
http://www.cygwin.com/ml/crossgcc/2011-05/msg00054.html

Anthony's report to the ppl-devel list:
http://www.cs.unipr.it/pipermail/ppl-devel/2011-May/017450.html

Roberto's reply with a link to the fix in the PPL git repo:
http://www.cs.unipr.it/pipermail/ppl-devel/2011-May/017455.html

Signed-Off-By: Anthony Foiani <anthony.foiani@gmail.com>
(transplanted from 139b85d70b623e51f7585e7c64ecb8c6a6cf4567) 
     1 diff -ru eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S

     2 --- eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S	2007-04-13 08:35:45.000000000 -0700

     3 +++ eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S	2009-05-06 16:52:04.000000000 -0700

     4 @@ -112,11 +112,13 @@

     5  	clrrwi.	rALIGN, rLEN, 5

     6  	mtcrf	0x01, rLEN	/* 40th instruction from .align */

     7  

     8 +#ifndef BROKEN_PPC_8xx_CPU15

     9  /* Check if we can use the special case for clearing memory using dcbz.

    10     This requires that we know the correct cache line size for this

    11     processor.  Getting the __cache_line_size may require establishing GOT

    12     addressability, so branch out of line to set this up.  */

    13  	beq	cr1, L(checklinesize)

    14 +#endif

    15  

    16  /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.

    17     Can't assume that rCHR is zero or that the cache line size is either

    18 @@ -158,6 +160,7 @@

    19  	add	rMEMP, rMEMP, rALIGN

    20  	b	L(medium_tail2)	/* 72nd instruction from .align */

    21  

    22 +#ifndef BROKEN_PPC_8xx_CPU15

    23  	.align	5

    24  	nop

    25  /* Clear cache lines of memory in 128-byte chunks.

    26 @@ -191,6 +194,7 @@

    27  	bdnz	L(zloop)

    28  	beqlr	cr5

    29  	b	L(medium_tail2)

    30 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    31  

    32  	.align	5

    33  L(small):

    34 @@ -248,6 +252,7 @@

    35  	stw	rCHR, -8(rMEMP)

    36  	blr

    37  

    38 +#ifndef BROKEN_PPC_8xx_CPU15

    39  L(checklinesize):

    40  #ifdef SHARED

    41  	mflr	rTMP

    42 @@ -329,6 +334,7 @@

    43  L(handletail32):

    44  	clrrwi.	rALIGN, rLEN, 5

    45  	b	L(nondcbz)

    46 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    47  

    48  END (BP_SYM (memset))

    49  libc_hidden_builtin_def (memset)
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