gcc: add patch to fix PR37436
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Wed Aug 05 15:23:52 2009 +0200 (2009-08-05)
changeset 1460d02a50cc300d
parent 1459 aec371a30cf3
child 1461 35b30f8fb307
gcc: add patch to fix PR37436

When compiling some C++ code, GCC 4.3.x fails with an internal
compiler error. The bug report is available at
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37436. The included patch
is the one that has been merged in the trunk of gcc.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
patches/gcc/4.3.2/380-pr37436.patch
patches/gcc/4.3.3/380-pr37436.patch
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/patches/gcc/4.3.2/380-pr37436.patch	Wed Aug 05 15:23:52 2009 +0200
     1.3 @@ -0,0 +1,86 @@
     1.4 +gcc svn 142778:
     1.5 +
     1.6 +PR target/37436
     1.7 +* arm.c (arm_legitimate_index): Only accept addresses that are in
     1.8 +canonical form.
     1.9 +* predicates.md (arm_reg_or_extendqisi_mem_op): New predicate.
    1.10 +* arm.md (extendqihi2): Use arm_reg_or_extendqisi_mem_op predicate
    1.11 +for operand1.
    1.12 +(extendqisi2): Likewise.
    1.13 +(arm_extendqisi, arm_extendqisi_v6): Use arm_extendqisi_mem_op
    1.14 +predicate for operand1.
    1.15 +
    1.16 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.c gcc-4.3.3/gcc/config/arm/arm.c
    1.17 +--- gcc-4.3.3.orig/gcc/config/arm/arm.c	2008-06-11 07:52:55.000000000 -0300
    1.18 ++++ gcc-4.3.3/gcc/config/arm/arm.c	2009-05-21 16:06:45.000000000 -0300
    1.19 +@@ -3769,6 +3769,7 @@
    1.20 +       rtx xop1 = XEXP (x, 1);
    1.21 + 
    1.22 +       return ((arm_address_register_rtx_p (xop0, strict_p)
    1.23 ++	       && GET_CODE(xop1) == CONST_INT
    1.24 + 	       && arm_legitimate_index_p (mode, xop1, outer, strict_p))
    1.25 + 	      || (arm_address_register_rtx_p (xop1, strict_p)
    1.26 + 		  && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
    1.27 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.md gcc-4.3.3/gcc/config/arm/arm.md
    1.28 +--- gcc-4.3.3.orig/gcc/config/arm/arm.md	2007-09-04 01:44:47.000000000 -0300
    1.29 ++++ gcc-4.3.3/gcc/config/arm/arm.md	2009-05-21 16:06:45.000000000 -0300
    1.30 +@@ -4199,7 +4199,7 @@
    1.31 + 
    1.32 + (define_expand "extendqihi2"
    1.33 +   [(set (match_dup 2)
    1.34 +-	(ashift:SI (match_operand:QI 1 "general_operand" "")
    1.35 ++	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
    1.36 + 		   (const_int 24)))
    1.37 +    (set (match_operand:HI 0 "s_register_operand" "")
    1.38 + 	(ashiftrt:SI (match_dup 2)
    1.39 +@@ -4224,7 +4224,7 @@
    1.40 + 
    1.41 + (define_insn "*arm_extendqihi_insn"
    1.42 +   [(set (match_operand:HI 0 "s_register_operand" "=r")
    1.43 +-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))]
    1.44 ++	(sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
    1.45 +   "TARGET_ARM && arm_arch4"
    1.46 +   "ldr%(sb%)\\t%0, %1"
    1.47 +   [(set_attr "type" "load_byte")
    1.48 +@@ -4235,7 +4235,7 @@
    1.49 + 
    1.50 + (define_expand "extendqisi2"
    1.51 +   [(set (match_dup 2)
    1.52 +-	(ashift:SI (match_operand:QI 1 "general_operand" "")
    1.53 ++	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
    1.54 + 		   (const_int 24)))
    1.55 +    (set (match_operand:SI 0 "s_register_operand" "")
    1.56 + 	(ashiftrt:SI (match_dup 2)
    1.57 +@@ -4267,7 +4267,7 @@
    1.58 + 
    1.59 + (define_insn "*arm_extendqisi"
    1.60 +   [(set (match_operand:SI 0 "s_register_operand" "=r")
    1.61 +-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))]
    1.62 ++	(sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
    1.63 +   "TARGET_ARM && arm_arch4 && !arm_arch6"
    1.64 +   "ldr%(sb%)\\t%0, %1"
    1.65 +   [(set_attr "type" "load_byte")
    1.66 +@@ -4278,7 +4278,8 @@
    1.67 + 
    1.68 + (define_insn "*arm_extendqisi_v6"
    1.69 +   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
    1.70 +-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))]
    1.71 ++	(sign_extend:SI
    1.72 ++	 (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
    1.73 +   "TARGET_ARM && arm_arch6"
    1.74 +   "@
    1.75 +    sxtb%?\\t%0, %1
    1.76 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/predicates.md gcc-4.3.3/gcc/config/arm/predicates.md
    1.77 +--- gcc-4.3.3.orig/gcc/config/arm/predicates.md	2007-08-02 07:49:31.000000000 -0300
    1.78 ++++ gcc-4.3.3/gcc/config/arm/predicates.md	2009-05-21 16:06:45.000000000 -0300
    1.79 +@@ -234,6 +234,10 @@
    1.80 +        (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
    1.81 + 					      0)")))
    1.82 + 
    1.83 ++(define_special_predicate "arm_reg_or_extendqisi_mem_op"
    1.84 ++  (ior (match_operand 0 "arm_extendqisi_mem_op")
    1.85 ++       (match_operand 0 "s_register_operand")))
    1.86 ++
    1.87 + (define_predicate "power_of_two_operand"
    1.88 +   (match_code "const_int")
    1.89 + {
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/patches/gcc/4.3.3/380-pr37436.patch	Wed Aug 05 15:23:52 2009 +0200
     2.3 @@ -0,0 +1,86 @@
     2.4 +gcc svn 142778:
     2.5 +
     2.6 +PR target/37436
     2.7 +* arm.c (arm_legitimate_index): Only accept addresses that are in
     2.8 +canonical form.
     2.9 +* predicates.md (arm_reg_or_extendqisi_mem_op): New predicate.
    2.10 +* arm.md (extendqihi2): Use arm_reg_or_extendqisi_mem_op predicate
    2.11 +for operand1.
    2.12 +(extendqisi2): Likewise.
    2.13 +(arm_extendqisi, arm_extendqisi_v6): Use arm_extendqisi_mem_op
    2.14 +predicate for operand1.
    2.15 +
    2.16 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.c gcc-4.3.3/gcc/config/arm/arm.c
    2.17 +--- gcc-4.3.3.orig/gcc/config/arm/arm.c	2008-06-11 07:52:55.000000000 -0300
    2.18 ++++ gcc-4.3.3/gcc/config/arm/arm.c	2009-05-21 16:06:45.000000000 -0300
    2.19 +@@ -3769,6 +3769,7 @@
    2.20 +       rtx xop1 = XEXP (x, 1);
    2.21 + 
    2.22 +       return ((arm_address_register_rtx_p (xop0, strict_p)
    2.23 ++	       && GET_CODE(xop1) == CONST_INT
    2.24 + 	       && arm_legitimate_index_p (mode, xop1, outer, strict_p))
    2.25 + 	      || (arm_address_register_rtx_p (xop1, strict_p)
    2.26 + 		  && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
    2.27 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/arm.md gcc-4.3.3/gcc/config/arm/arm.md
    2.28 +--- gcc-4.3.3.orig/gcc/config/arm/arm.md	2007-09-04 01:44:47.000000000 -0300
    2.29 ++++ gcc-4.3.3/gcc/config/arm/arm.md	2009-05-21 16:06:45.000000000 -0300
    2.30 +@@ -4199,7 +4199,7 @@
    2.31 + 
    2.32 + (define_expand "extendqihi2"
    2.33 +   [(set (match_dup 2)
    2.34 +-	(ashift:SI (match_operand:QI 1 "general_operand" "")
    2.35 ++	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
    2.36 + 		   (const_int 24)))
    2.37 +    (set (match_operand:HI 0 "s_register_operand" "")
    2.38 + 	(ashiftrt:SI (match_dup 2)
    2.39 +@@ -4224,7 +4224,7 @@
    2.40 + 
    2.41 + (define_insn "*arm_extendqihi_insn"
    2.42 +   [(set (match_operand:HI 0 "s_register_operand" "=r")
    2.43 +-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))]
    2.44 ++	(sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
    2.45 +   "TARGET_ARM && arm_arch4"
    2.46 +   "ldr%(sb%)\\t%0, %1"
    2.47 +   [(set_attr "type" "load_byte")
    2.48 +@@ -4235,7 +4235,7 @@
    2.49 + 
    2.50 + (define_expand "extendqisi2"
    2.51 +   [(set (match_dup 2)
    2.52 +-	(ashift:SI (match_operand:QI 1 "general_operand" "")
    2.53 ++	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
    2.54 + 		   (const_int 24)))
    2.55 +    (set (match_operand:SI 0 "s_register_operand" "")
    2.56 + 	(ashiftrt:SI (match_dup 2)
    2.57 +@@ -4267,7 +4267,7 @@
    2.58 + 
    2.59 + (define_insn "*arm_extendqisi"
    2.60 +   [(set (match_operand:SI 0 "s_register_operand" "=r")
    2.61 +-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))]
    2.62 ++	(sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
    2.63 +   "TARGET_ARM && arm_arch4 && !arm_arch6"
    2.64 +   "ldr%(sb%)\\t%0, %1"
    2.65 +   [(set_attr "type" "load_byte")
    2.66 +@@ -4278,7 +4278,8 @@
    2.67 + 
    2.68 + (define_insn "*arm_extendqisi_v6"
    2.69 +   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
    2.70 +-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))]
    2.71 ++	(sign_extend:SI
    2.72 ++	 (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
    2.73 +   "TARGET_ARM && arm_arch6"
    2.74 +   "@
    2.75 +    sxtb%?\\t%0, %1
    2.76 +diff -Nura gcc-4.3.3.orig/gcc/config/arm/predicates.md gcc-4.3.3/gcc/config/arm/predicates.md
    2.77 +--- gcc-4.3.3.orig/gcc/config/arm/predicates.md	2007-08-02 07:49:31.000000000 -0300
    2.78 ++++ gcc-4.3.3/gcc/config/arm/predicates.md	2009-05-21 16:06:45.000000000 -0300
    2.79 +@@ -234,6 +234,10 @@
    2.80 +        (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
    2.81 + 					      0)")))
    2.82 + 
    2.83 ++(define_special_predicate "arm_reg_or_extendqisi_mem_op"
    2.84 ++  (ior (match_operand 0 "arm_extendqisi_mem_op")
    2.85 ++       (match_operand 0 "s_register_operand")))
    2.86 ++
    2.87 + (define_predicate "power_of_two_operand"
    2.88 +   (match_code "const_int")
    2.89 + {